////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012 Kentaro Sekimoto  All rights reserved.
////////////////////////////////////////////////////////////////////////////

#include <tinyhal.h>
#include "..\..\..\..\..\DeviceCode\Targets\Native\FM3\DeviceCode\FM3.h"

//--//

#ifdef MB9BF506N

// CLK  P3F
// DI   P3C
// CS   P3D
// RS   P10
volatile unsigned int* spisw_rs = &(bFM3_GPIO_PDOR1_P0);
volatile unsigned int* spisw_mosi = &(bFM3_GPIO_PDOR3_PC);
volatile unsigned int* spisw_ck = &(bFM3_GPIO_PDOR3_PF);
volatile unsigned int* spisw_cs = &(bFM3_GPIO_PDOR3_PD);

void SPISW_GPIO_Initialize(void)
{
    bFM3_GPIO_PFR1_P0 = 0;
    bFM3_GPIO_PFR3_PC = 0;
    bFM3_GPIO_PFR3_PF = 0;
    bFM3_GPIO_PFR3_PD = 0;

    bFM3_GPIO_DDR1_P0 = 1;
    bFM3_GPIO_DDR3_PC = 1;
    bFM3_GPIO_DDR3_PF = 1;
    bFM3_GPIO_DDR3_PD = 1;
}

#else

#define SPISWPIN	0

#if (SPISWPIN == 0)
// CLK  PF2
// DI   PF1
// CS   P7D
// RS   PF0
// RES  P3F
volatile unsigned int* spisw_rs = &(bFM3_GPIO_PDORF_P0);
volatile unsigned int* spisw_mosi = &(bFM3_GPIO_PDORF_P1);
volatile unsigned int* spisw_ck = &(bFM3_GPIO_PDORF_P2);
volatile unsigned int* spisw_cs = &(bFM3_GPIO_PDOR7_PD);
volatile unsigned int* spisw_res = &(bFM3_GPIO_PDOR3_PF);
#elif (SPISWPIN == 1)
// CLK  P40
// DI   P41
// CS   P42
// RS   P43
// RES	P44
volatile unsigned int* spisw_rs = &(bFM3_GPIO_PDOR4_P3);
volatile unsigned int* spisw_mosi = &(bFM3_GPIO_PDOR4_P1);
volatile unsigned int* spisw_ck = &(bFM3_GPIO_PDOR4_P0);
volatile unsigned int* spisw_cs = &(bFM3_GPIO_PDOR4_P2);
volatile unsigned int* spisw_res = &(bFM3_GPIO_PDOR4_P4);
#elif (SPISWPIN == 2)
// CLK  P3F
// DI   P3C
// CS   P3D
// RS   P10
volatile unsigned int* spisw_rs = &(bFM3_GPIO_PDOR1_P0);
volatile unsigned int* spisw_mosi = &(bFM3_GPIO_PDOR3_PC);
volatile unsigned int* spisw_ck = &(bFM3_GPIO_PDOR3_PF);
volatile unsigned int* spisw_cs = &(bFM3_GPIO_PDOR3_PD);
volatile unsigned int* spisw_res = (volatile unsigned int* )0;
#else
// CLK  P31
// DI   P32
// CS   P30
// RS   P34
// RES  P35
volatile unsigned int* spisw_rs = &(bFM3_GPIO_PDOR3_P4);
volatile unsigned int* spisw_mosi = &(bFM3_GPIO_PDOR3_P2);
volatile unsigned int* spisw_ck = &(bFM3_GPIO_PDOR3_P1);
volatile unsigned int* spisw_cs = &(bFM3_GPIO_PDOR3_P0);
volatile unsigned int* spisw_res = &(bFM3_GPIO_PDOR3_P5);
#endif

void SPISW_GPIO_Initialize(void)
{
#if (SPISWPIN == 0)
    bFM3_GPIO_PFRF_P0 = 0;
    bFM3_GPIO_PFRF_P1 = 0;
    bFM3_GPIO_PFRF_P2 = 0;
    bFM3_GPIO_PFR7_PD = 0;
    bFM3_GPIO_PFR3_PF = 0;

    bFM3_GPIO_DDRF_P0 = 1;
    bFM3_GPIO_DDRF_P1 = 1;
    bFM3_GPIO_DDRF_P2 = 1;
    bFM3_GPIO_DDR7_PD = 1;
    bFM3_GPIO_DDR3_PF = 1;
#elif (SPISWPIN == 1)
    bFM3_GPIO_PFR4_P0 = 0;
    bFM3_GPIO_PFR4_P1 = 0;
    bFM3_GPIO_PFR4_P2 = 0;
    bFM3_GPIO_PFR4_P3 = 0;
    bFM3_GPIO_PFR4_P4 = 0;

    bFM3_GPIO_DDR4_P0 = 1;
    bFM3_GPIO_DDR4_P1 = 1;
    bFM3_GPIO_DDR4_P2 = 1;
    bFM3_GPIO_DDR4_P3 = 1;
    bFM3_GPIO_DDR4_P4 = 1;
#elif (SPISWPIN == 2)
    bFM3_GPIO_PFR3_P4 = 0;
    bFM3_GPIO_PFR3_P2 = 0;
    bFM3_GPIO_PFR3_P1 = 0;
    bFM3_GPIO_PFR3_P0 = 0;
    bFM3_GPIO_PFR3_P5 = 0;

    bFM3_GPIO_DDR3_P4 = 1;
    bFM3_GPIO_DDR3_P2 = 1;
    bFM3_GPIO_DDR3_P1 = 1;
    bFM3_GPIO_DDR3_P0 = 1;
    bFM3_GPIO_DDR3_P5 = 1;
#else
#endif
}

#endif
